آمار
| تعداد نشریات | 31 |
| تعداد شماره‌ها | 734 |
| تعداد مقالات | 8,011 |
| تعداد مشاهده مقاله | 9,810,187 |
| تعداد دریافت فایل اصل مقاله | 9,290,068 |
یک مقایسه کننده قفل‌شده تمام تفاضلی مجهز به روش نوین حذف آفست | ||
| مجله مهندسی برق دانشگاه تبریز | ||
| مقاله 37، دوره 48، شماره 4 - شماره پیاپی 86، زمستان 1397، صفحه 1831-1842 اصل مقاله (1.32 MB) | ||
| نوع مقاله: مقاله پژوهشی | ||
| نویسندگان | ||
سعید نقوی؛ سید ادیب ابریشمی‌فر 
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| دانشکده مهندسی برق - دانشگاه علم و صنعت ایران | ||
| چکیده | ||
| در این مقاله یک مدار مقایسه‌کننده قفل‌شده تمام تفاضلی با استفاده از روشی جدید برای حذف آفست معرفی شده است. مدار مقایسه‌کننده شامل سه‌طبقه کلی: طبقه پیش‌تقویت‌کننده، طبقه قفل‌کننده و مدارهای حذف آفست می‌باشد. تأثیر نویز کیک-بک در ورودی به‌طور قابل‌ملاحظه‌ای توسط بهره مدار پیش‌تقویت‌کننده طراحی‌شده کاهش داده شده است. هم‌چنین با استفاده از طبقه قفل‌کننده عمل بازتولید سیگنال سریع‌تر انجام شده و خروجی دیجیتال با نوسان کامل فراهم می‌شود. مزیت اصلی طبقه آخر یعنی مدار حذف آفست پیشنهادی این است که برای حذف آفست نیازی به ایجاد وقفه در عملکرد طبیعی مدار مقایسه‌کننده ندارد و درنتیجه سرعت بیش‌تری برای مقایسه قابل دست‌یابی خواهد بود. برای ارزیابی عملکرد مقایسه‌کننده پیشنهادی شبیه‌سازی‌ها با استفاده از فن‌آوری 0.18 انجام شده است. نتایج شبیه‌سازی نشان می‌دهند مقادیر آفست ناشی از طبقات پیش‌تقویت‌کننده و قفل‌کننده به‌طور قابل‌ملاحظه‌ای در ورودی کاهش یافته و آفست منتقل شده به ورودی بسیار ناچیز و در حدود 450 می‌باشد. مدار مقایسه‌کننده پیشنهادی با فرکانس کلاک MHz500 عمل مقایسه را انجام می‌دهد و توان مصرفی آن 373 از منبع تغذیه 1.8 ولتی می‌باشد. هم‌چنین تأخیر انتشار آن pS138 و نویز کیک-بک آن فقط mV 0.54 می‌باشد. | ||
| کلیدواژه‌ها | ||
| مقایسه‌کننده تمام تفاضلی؛ پیش‌تقویت‌کننده؛ مقایسه‌کننده قفل‌شده؛ مدارهای حذف آفست؛ نویز کیک-بک | ||
| عنوان مقاله [English] | ||
| A Fully Differential Latched Comparator with a Novel Offset Cancellation Technique | ||
| نویسندگان [English] | ||
| S. Naghavi؛ A. Abrishamifar | ||
| School of Electrical Engineering, Iran University of Science and Technology, Tehran, Iran | ||
| چکیده [English] | ||
| A Fully Differential latched comparator using a new offset cancellation technique is presented. The comparator consists of three stages: the input pre-amplifier, a latch stage and the offset cancellation circuitry. The kick-back noise can be significantly reduced by using a pre-amplifier stage. Also, the offset and noise of the latch and offset cancellation stages are attenuated by the gain of the pre-amplifier when referred to the input. Latches regenerate faster than pre-amplifiers and provide a full swing digital output for the comparator. The last stage is the offset cancellation circuitry. The main advantage of the proposed offset cancellation technique is that it does not need to make any interrupt in normal operation of comparator to eliminate offset error. In order to evaluate the performance of the comparator, simulations are performed in a 0.18µm standard CMOS technology. Simulation results show that the offset of the pre-amplifier and latch stages are significantly eliminated by this cancellation technique and only about 450µv offset voltage will be referred to the input. The proposed comparator operates at 500MHz clock frequency and dissipates 373µw from a 1.8v supply. Also, it has a propagation delay of 138ps and kick-back noise of 0.54mv. | ||
| کلیدواژه‌ها [English] | ||
| Fully differential comparator, Pre-amplifier, Latched comparator, Offset cancellation, kick-back noise | ||
| مراجع | ||
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[1] T. Shih, L. Der, S. H. Lewis, and P. J. Hurst, “A fully differential comparator using a switched-capacitor differencing circuit with common-mode rejection,” IEEE Journal of Solid-State Circuits, vol. 32, no. 2, pp. 250-253, 1997. [2] K. M. Lei, P. I. Mak, R. P. Martins, “Systematic analysis and cancellation of kick-back noise in a dynamic latched comparator,” Analog Integrated Circuits and Signal Processing, vol. 77, no.2, pp. 277-284, 2013. [3] K. L. J. Wong, Comparison of Digital Offset Compensation in Comparators, Master of Science thesis, University of California, 2002. [4] C. Brenneman, Circuit Design for Realization of a 16 bit 1MS/s Successive Approximation Register Analog-to-Digital Converter, Master of Science thesis, Worcester Polytechnic Institute, 2010. [5] J. Lu, J. Holleman, “A low-power high-precision comparator with time-domain bulk-tuned offset cancellation,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 60, no. 5, pp. 1158-1167, 2013. [6] H. J. Jeon, Y. B. Kim, “A novel low-power, low-offset, and high-speed CMOS dynamic latched comparator,” Analog Integrated Circuits and Signal Processing, vol. 77, no. 3, pp. 337-346, 2012. [7] J. He, S. Zhan, D. Chen, R. L. Geiger, “Analyses of static And dynamic random offset voltages in dynamic comparators, IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 56, no. 5, pp. 911-919, 2009. [8] A. Nikoozadeh, B. Murmann, “An analysis of latch comparator offset due to load capacitor mismatch,” IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 12, no. 53, pp. 1398-1402, 2006. [9] B. Razavi, Design of Analog CMOS Integrated Circuits, Mcgraw-Hill, 2001. [10] S. B. Mashhadi, R. Lotfi, “An offset cancellation technique for comparators using body-voltage trimming,” Analog Integrated Circuits and Signal Processing, vol. 73, no. 3, pp. 673-682, 2012. [11] H. J. Jeon, Y. B. Kim, “Offset voltage analysis of dynamic latched comparator,” IEEE 54th International Mid-west Symposium on Circuits and Systems (MWSCAS), pp. 1-4, 2011. [12] H. J. Jeon, Y. B. Kim, “A low-offset high-speed double-tail dual-rail dynamic latched comparator,” Proceedings of the 20th symposium on Great lakes symposium on VLSI, pp. 45-48, 2010. [13] K. Kotani, T. Shibata and T. Ohmi, “CMOS charge-transfer preamplifier for offset-fluctuation cancellation in low-power A/D converters,” IEEE Journal of Solid-State Circuits, vol. 33, no. 5, pp. 762-769, 1998. [14] X. Zhu, Y. Chen, M. Kibune, Y. Tomita, T. Hamada, H. Tamura, S. Tsukamoto, and T. Kuroda, “A dynamic offset control technique for comparator design in scaled CMOS technology,” IEEE Custom Integrated Circuits Conference (CICC), pp. 495-498, 2008. [15] H. Zhang, Y. Qin, and Z. Hong, “A 1.8-V 770-nW bio potential acquisition system for portable applications,” IEEE Biomedical Circuits and Systems Conference (BioCAS), pp. 93-96, 2009. [16] C.-H. Chan, Y. Zhu, U.-F. Chio, S.-W. Sin, S.-P. U., and R. P. Martins, “A reconfigurable low-noise dynamic comparator with offset calibration in 90 nm CMOS,” IEEE Asian Solid-State Circuits Conference (A-SSCC), pp. 233-236, 2011. [17] M. Miyahara, Y. Asada, D. Paik, and A. Matsuzawa, “A low-noise self-calibrating dynamic comparator for high-speed ADCs,” IEEE Asian Solid-State Circuits Conference (A-SSCC), pp. 269-272, 2008. [18] Y. L. Wong, M. H. Cohen, and P. A. Abshire, “A floating-gate comparator with automatic offset adaptation for 10-bit data conversion,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 52, no. 7, pp. 1316-1326, 2005. [19] Y. L. Wong, M. H. Cohen, and P. A. Abshire, “A 1.2-GHz comparator with adaptable offset in 0.35µm CMOS,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 55, no. 9, pp. 2584-2594, 2008. [20] J. Yao, J. Liu, and H. Lee, “Bulk voltage trimming offset calibration for high-speed flash ADCs,” IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 57, no. 2, pp. 110-114, 2010. [21] Y. Degerli, N. Fourches, M. Rouger, and P. Lutz, “Low-power auto zeroed high-speed comparator for the readout chain of a CMOS monolithic active pixel sensor based vertex detector,” IEEE Transactions on nuclear science, vol. 50, no. 5, pp. 1709-1717, 2003. [22] S. A. P. Haddad, I. Nascimento, “A high-speed low-power CMOS comparator using auto-zero offset cancellation technique,” Proceedings of the 24th symposium on Integrated circuits and systems design, pp. 35-38, 2011. [23] H. Zumbahlen, Linear circuit design handbook, Norwood: Analog Devices, 2008. [24] A. Graupner, “A Methodology for the Offset Simulation of Comparators,” The Designer's Guide Community, vol. 1, 2006. [25] Imran Ahmed, Pipelined ADC design and enhancement techniques, Springer Science Business Media, 2010. [26] A. Khorami, M. Sharifkhani, High-speed low-power comparator for analog to digital converters,” AEU-International Journal of Electronics and Communications, vol. 70, no.7, pp. 886-894, 2016. [27] H. J. Achigui, C. Fayomi, D. Massicotte, M. Boukadouma, “Low-voltage, high-speed CMOS analog Latched voltage comparator using the flipped voltage follower as input stage,” Microelectronics Journal, vol. 42, no. 5, pp. 785-789, 2011. [28] K. D. Sadeghipour, “An improved low offset latch comparator for high-speed ADCs,” Analog Integrated Circuits and Signal Processing, vol. 66, no. 2, pp. 205-212, 2011. [29] M. M. Khanghah, K. D. Sadeghipour, “A 0.5V offset cancelled latch comparator in standard 0.18µm CMOS process,” Analog Integrated Circuits and Signal Processing, vol. 66, no. 2, pp. 161-169, 2014. | ||
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آمار تعداد مشاهده مقاله: 41 تعداد دریافت فایل اصل مقاله: 111 |
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