یک فلیپ فلاپ غیر فرار دو حالته مبتنی بر اثر برهمکنش اسپین برای تحقق محاسبات غیر فرار

[1] رامین رجایی «طراحی یک فلیپ فلاپ کم توان، پرسرعت و مصون از خطای نرم برای فن آوری های نانومتری‎»، مجله مهندسی برق دانشگاه تبریز، دوره 50، شماره 1، صفحات 137-146، 1399.

[2] بهشید شایسته، وصال حکمی، سید اکبر مصطفوی، احمد اکبری « ارائه روشی نوین برای محاسبه اعتماد در کاربردهای اینترنت اشیاء»، مجله مهندسی برق دانشگاه تبریز، دوره 50، شماره 2، صفحات 755 - 743 ، 1399.

[3] Guo, J. Yin, Y. Bai, D. Zhu, K. Shi, G. Wang, K. Cao, and W. Zhao, ‘‘Spintronics for energy-efficient computing: An overview and outlook,’’ Proc. IEEE, vol. 109, no. 8, pp. 1398–1417, Aug. 2021.

[4] Barla, V. K. Joshi, and S. Bhat, ‘‘A novel low power and reduced transistor count magnetic arithmetic logic unit using hybrid STTMTJ/CMOS circuit,’’ IEEE Access, vol. 8, pp. 6876–6889, 2020.

[5] Thapliyal, F. Sharifi, and S. D. Kumar, ‘‘A Highly Reliable, Dynamic Logic-Based Hybrid MTJ/CMOS Magnetic Full Adder for High-Performance and Low-Power Application,’’ IEEE Transactions on Magnetics, vol. 58, no. 5, pp. 1–8, 2022.

[6] Raouf and S. Timarchi, ‘‘Non-volatile and high-performance cascadable spintronic full-adder with no sensitivity to input scheduling,’’ IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 70, no. 6, pp. 2236–2240, Jun. 2023.

[7] Yang, K. He, Z. Zhang, and Y. Lu, ‘‘A novel computing-in-memory platform based on hybrid spintronic/CMOS memory. IEEE Transactions on Electron Devices, vol. 69, no. 4, pp.1698-1705, 2022.

[8] Jamshidi, A.Patooghy, and M.Fazeli, ‘‘MagCiM: A Flexible and Non-Volatile Computing-in-Memory Processor for Energy-Efficient Logic Computation,’’ IEEE Access, vol. 10, pp.35445-35459, 2022.

[9] Wang, Y. Liu, C. Wang, Z. Li, X. Sheng, H. G. Lee, N. Chang, and H. Yang, ‘‘Storage-less and converter-less photovoltaic energy harvesting with maximum power point tracking for Internet of Things,’’ IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 35, no. 2, pp. 173–186, Feb. 2016.

[10] Jabeur, G. Di Pendina, F. Bernard-Granger, and G. Prenat, “Spin orbit torque non-volatile flip-flop for high speed and low energy applications,” IEEE electron device letters, vol. 35, no. 3, pp. 408–410, 2014.

[11] Wang, W. Zhao, E. Deng, Y. Zhang, and J.-O. Klein, “Magnetic non-volatile flip-flop with spin-hall assistance,” physic status solidi (RRL)–Rapid Research Letters, vol. 9, no. 6, pp. 375–378, 2015.

[12] Bishnoi, F. Oboril, and M. B. Tahoori, “Non-volatile non- shadow flip-flop using spin orbit torque for efficient normally-off computing,” in 2016 21st Asia and South Pacific Design Automation Conference (ASP-DAC). IEEE, 2016, pp. 769–774.

[13] Seo, X. Fong, and K. Roy, “Fast and disturb-free nonvolatile flip-flop using complementary polarizer mtj,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 25, no. 4 pp. 1573–1577, 2016.

[14] Verma, R. Paul, and M. Shukla, “Non-volatile latch compatible with static and dynamic CMOS for logic in memory applications,” IEEE Transactions on Magnetics,  vol. 58, no. 4, pp. 1–8, 2022.

[15] Madhura, “A review on low power vlsi design models in various circuits,” J. Electron, vol. 4, pp.74-81, 2022.

[16] Rangaprasad, VK.Joshi, “A Fully Non-Volatile Reconfigurable Magnetic Arithmetic Logic Unit Based on Majority Logic,” IEEE Access, vol. 11, pp. 118944-118961, 2023.

[17] Shukla, P. Kumar, and P. K. Misra, “An energy efficient, mismatch tolerant offset compensating hybrid MTJ/CMOS magnetic full adder,” IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 69, no. 11, pp. 4548–4552, Nov. 2022.

[18] Ali, F. Li, S. Y. Lua, and C.-H. Heng, “Compact spin transfer torque non-volatile flip flop design for power-gating architecture,” in 2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS). IEEE, 2016, pp. 119–122.

[19] Mitchell, M. Hunt, C. McCartney, and F. Ho, “Implementation of low-power, non-volatile latch utilising ferroelectric transistor,” Electronics Letters, vol. 51, no. 23, pp. 1884–1886, 2015.

[20] Jamshidi, “NVRH-LUT: A nonvolatile radiation-hardened hybrid MTJ/CMOS-based look-up table for ultra low power and highly reliable FPGA designs.” Turkish Journal of Electrical Engineering and Computer Sciences, vol. 27, no. 6, pp.4486-4501, 2019.

[21] Amirany, K. Jafari, and M.H. Moaiyeri, “High-performance radiation-hardened spintronic retention latch and flip-flop for highly reliable processors,”  IEEE Transactions on Device and Materials Reliability, vol. 21, no. 2, pp.215-223, 2021.

[22] Ryu, J. Kim, J. Jung, J. P. Kim, S. H. Kang, and S.-O. Jung, “A magnetic tunnel junction based zero standby leakage current retention flip-flop,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 20, no. 11, pp. 2044–2053, 2011.

[23] Lakys, W. Zhao, J.-O. Klein, and C. Chappert, “Low power, high reliability magnetic flip-flop,” Electronics letters, vol. 46, no. 22, pp. 1493–1494, 2010.

[24] Rajaei, “A reliable, low power and nonvolatile mtj-based flipflop for advanced nanoelectronics,” Journal of Circuits, Systems and Computers, vol. 27, no. 13, p. 1850205, 2018.

[25] Kimura, T. Fuchikami, K. Maramoto, Y. Fujimori, S. Izumi, H. Kawaguchi, and M. Yoshimoto, “A 2.4 pj ferroelectric-based non-volatile flip-flop with 10-year data retention capability,” in 2014 IEEE Asian Solid-State Circuits Conference (A-SSCC). IEEE, 2014, pp. 21–24.

[26] Qazi, A. Amerasekera, and A. P. Chandrakasan, “A 3.4-pj feram-enabled d flip-flop in 0.13um cmos for nonvolatile processing in digital systems,” IEEE Journal of Solid-State Circuits, vol. 49, no. 1, pp. 202–211, 2013.

[27] Izumi, H. Kawaguchi, M. Yoshimoto, H. Kimura, T. Fuchikami, K. Marumoto, and Y. Fujimori, “A ferroelectric based non-volatile flip-flop for wearable healthcare systems,” in 2015 15th NonVolatile Memory Technology Symposium (NVMTS). IEEE, 2015, pp. 1–4.

[28] Barla,V. K. Joshi, and S. Bhat, ‘‘Fully nonvolatile hybrid full adder based on SHE+STT-MTJ/CMOS LIM architecture,’’ IEEE Trans. Magn., vol. 58, no. 9, pp. 1–11, Sep. 2022.

[29] Na, K. Ryu, J. Kim, S.-O. Jung, J. P. Kim, and S. H. Kang, “High- performance low-power magnetic tunnel junction based non- volatile flip-flop,” in 2014 IEEE International Symposium on Circuits and Systems (ISCAS). IEEE, 2014, pp. 1953–1956.

[30] M. Bromberg, D.H. Morris, L. Pileggi, and J.G. Zhu, “Novel STT-MTJ Device Enabling All-Metallic Logic Circuits,” IEEE transactions on Magnetics, pp. 3215-3218, 2012.

[31] Kumar, D. Divyanshu, D. Khan, S. Amara, and Y. Massoud, ‘‘Polymorphic hybrid CMOS-MTJ logic gates for hardware security applications,’’ Electronics, vol. 12, no. 4, p. 902, Feb. 2023.

[32] Ma, S. Li, V. Narayanan, and Y. Xie, “Nonvolatile processor architecture exploration for energy-harvesting application scenarios,” in Embedded, Cyber-Physical, and IoT Systems. Springer, 2020, pp. 175–202.

[33] Roohi and R. F. DeMara, “Nv-clustering: Normally-off computing using non-volatile datapaths,” IEEE Transactions on Computers, vol. 67, no. 7, pp. 949–959, 2018.

[34] Ali, F. Li, S. Y. Lua, and C.-H. Heng, “Energy-and area efficient spin–orbit torque nonvolatile flip-flop for power gating architecture,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 26, no. 4, pp. 630–638, 2018.

[35] Wang, Z. Wang, Y. Xu, B. Wu, and W. Zhao, “Erase-hidden and drivability-improved magnetic non-volatile flip-flops with nand spin devices,” IEEE Transactions on Nanotechnology, vol. 19, pp. 446–454, 2020.

[36] Park, “Hybrid non-volatile flip-flops using spin-orbit-torque (sot) magnetic tunnel junction devices for high integration and low energy power-gating applications,” Electronics, vol. 9, no. 9, p. 1406, 2020.

[37] Garg, and S. Wairya, “Performance Evaluation of Full Adder Using Magnetic Tunnel Junction,” In Proceedings of International Conference on Recent Trends in Computing, pp. 517-526, 2021.

[38] Rangaprasad S,VK. Joshi and BK. Kaushik, “A fully non-volatile reconfigurable magnetic decoder,” Microelectronics Journal, vol. 26, no. 2, pp. 294–307, 2023.

[39] Jamshidi, and M.Fazeli, ‘‘Pure magnetic logic circuits: A reliability analysis,’’ IEEE Transactions on Magnetics, vol. 54, no. 10, pp.1-10, 2018.