مدار پویای جدید برای طراحی رجیستر فایل‌های سرعت- ‌بالا

[1] M. Sharroush, E. Badry, “Proposed time-mode wide fan-in NAND and NOR gates”, International Journal of Circuit Theory and Applications, pp. 1– 34, 2023.

[2] Kumar, R. K. Nagaria, “Reduction of variation and leakage in wide fan-in OR Logic domino gate”, Integration, the VLSI Journal, vol. 89, pp. 229-240, 2023.

[3] Kumar, R. K. Nagaria, “A new process variation and leakage-tolerant domino circuit for wide fan-in OR gates”, Analog Integrated Circuits and Signal Processing, vol. 102, no. 2, pp. 9-25, 2020.

[4] H. Anis, M. W. Allam, M. I. Elmasry, “Energy-efficient noise-tolerant dynamic styles for scaled-down CMOS and MTCMOS technologies”, IEEE Transaction on Very Large Scale Integration (VLSI) Systems, vol.10, pp. 71-78, 2002.

[5] Alvandpour, R. Krishnamurthy, K. Sourrty, S. Y. Borkar, “A sub-130-nm conditional-keeper technique”, IEEE Journal of Solid-State Circuits, vol. 37,pp. 633– 638, 2002.

[6] Lih, N. Tzartzanis, W. W. Walker, “A leakage current replica keeper for dynamic circuits”, IEEE Journal of Solid-State Circuits, vol. 42, pp. 48– 55, 2007.

[7] Suzuki, C. H. Kim, K. Roy, “Fast tag comparator using diode partitioned domino for 64-bit microprocessors”, IEEE Transaction on Very Large Scale Integration (VLSI) Systems, vol. 54, pp. 322- 328, 2007.

[8] A. Angeline, V.S. K. Bhaaskaran, “Speed enhancement techniques for clock-delayed dual keeper domino logic style”, International Journal of Electronics, vol. 107, pp.1239-1253, 2020.

[9] Kannan, R. Rangarajan, “Low power noise immune node voltage comparison keeper design for high speed architectures”, Microprocessors and Microsystems, vol. 77, pp. 103192, 2020.

[10] K. Pandey, T.K. Gupta, A. Gupta, D. Pandey, “Keeper effect on nano scale silicon domino logic transistors”, Silicon, vol. 14, pp. 6769–6776, 2022.[11] Asyaei, “New dynamic logic style for energy efficient tag comparators”, Microprocessors and Microsystems Journal, Vol. 90, pp. 104522, 2022.

[11] M. Asyaei, “New dynamic logic style for energy efficient tag comparators”, Microprocessors and Microsystems Journal, Vol. 90, pp. 104522, 2022.

[12] Singhal, A. Mehra, “Gated clock and revised keeper (GCRK) domino logic design in 16 nm CMOS technology”, IETE Journal of Research, vol. 69, no. 3, pp. 1686-1693, 2023.

[13] J. Kandpal, T. R. Pokhrel, S. Saini, A. Majumder, “A variation resilient keeper design for high performance domino logic applications”, Integration, the VLSI Journal, 88, pp. 1-9, 2023.

[14] Alioto, G. Palumbo, M. Pennisi, “Understanding the effect of process variations on the delay of static and domino logic”, IEEE Transaction on Very Large Scale Integration (VLSI) Systems, vol. 18, pp. 697- 710, 2010.

[15] محمد آسیایی، «مدار دینامیکی جدید برای طراحی مقایسه‌کننده‌ نشانه توان پایین» مجله مهندسی برق دانشگاه تبریز، جلد 49، شماره 1، صفحات 1-11، بهار 1398.

[16] Peiravi, M. Asyaei, “Current-comparison-based domino: new low-leakage high-speed domino circuit for wide fan-in gates”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 21, no. 5, pp. 934-943, 2013.

[17] محمد آسیایی، «دومینو مبتنی بر مقایسه جریان ارتقاءیافته برای طراحی گیت‌های عریض توان پایین» مجله مهندسی برق دانشگاه تبریز، جلد 47، شماره 1، صفحات 1-10، بهار 1396.

[18] Asyaei, “A new low-power dynamic circuit for wide fan-in gates”, Integration, the VLSI Journal, vol. 60, pp. 263-271, 2018.

[19] Krishnamurthy, A. Alvandpour, G. Balamurugan, N. R. Shanbhag, K. Soumyanath, S. Y. Borkar “A 130-nm 6-GHz 256´32 bit leakage-tolerant register file”, IEEE Journal of Solid-State Circuits, vol. 37, pp. 624– 632, 2002.