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Reference spur suppression in the Integer-N frequency synthesizers by reducing periodic ripples amplitude on the VCO control voltage | ||
| مجله مهندسی برق دانشگاه تبریز | ||
| مقاله 7، دوره 51، شماره 1 - شماره پیاپی 95، اردیبهشت 1400، صفحه 61-69 اصل مقاله (1.66 M) | ||
| نوع مقاله: علمی-پژوهشی | ||
| نویسندگان | ||
| S. Jahangirzadeh؛ A. Amirabadi؛ A. Farrokhi* | ||
| Department of Electrical Engineering, South Tehran Branch, Islamic Azad University, Tehran, Iran. | ||
| چکیده | ||
| To achieve a low reference spur for an Integer-N frequency synthesizer, a new spur reducing technique was proposed. To reduce the size of periodic ripples on the VCO control voltage, the low pass filter, and the charge pump were added with a spur reduction system. By lowering the amplitude of the periodic ripple on the VCO control voltage, we managed to lower the reference spur. The introduced technique removes the necessity to decrease bandwidth and CVO gain reference spur suppressing. To demonstrate the effectiveness of the proposed structure, a 2.06 – 2.22 GHz frequency synthesizer was used and the 180-nm CMOS technology was used for post-layout simulation. The proposed frequency synthesizer represents the reference spur of -85.84 dBc at 20 MHz offset and phase noise of -108dBc/Hz at 200 kHz offset frequency also it is locked after 2.8us while occupied 0.35 mm2 of the chip area. | ||
| کلیدواژه‌ها | ||
| Spur suppression؛ reference spur؛ voltage controlled oscillator (VCO)؛ and integer-N frequency synthesizer | ||
| مراجع | ||
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[1] T.H. Lin, W. J. Kaiser, “A 900-MHz 2.5-mA CMOS frequency synthesizer with an automatic SC tuning loop”, IEEE Journal of Solid-State Circuits, vol. 36, no. 3, pp. 424-431, 2001. [2] S. Pellerano, S. Levantino, C. Samori, A. L. Lacaita, “A 13.5-mW 5-GHz frequency synthesizer with dynamic-Logic frequency divider”, IEEE Journal of Solid-State Circuits, vol. 39, no. 2, pp. 378–383, 2004. [3] F. Herzel, G. Fischer, H. Gustat, “An integrated CMOS RF synthesizer for 802.11a wireless LAN”, IEEE Journal of Solid-State Circuits, vol. 38, no. 10, pp. 1767–1770, 2003. [4] X. Gao, E. Klumperink, G. Socci, M. Bohsali, B. Nauta, “Spur reduction techniques for phase-locked loops exploiting a sub-sampling phase detector”, IEEE Journal of Solid-State Circuits, vol. 45, no. 9, pp. 1809–1821, 2010. [5] X. Li, J. Zhang, Y. Zhang, W. Wang, H. Liu, C. Lu, “A 5.7–6.0 GHz CMOS PLL with low phase noise and −68 dBc reference spur”, International Journal of Electronics and Communications, vol. 85, pp. 23–31, 2018. [6] A. Kraal, F. Behbahani, A. A. Abidi, “RF-CMOS oscillators with switched tuning”, Proceedings of the IEEE 1998 Custom Integrated Circuits Conference, May 1998, Santa Clara, CA, USA, USA, pp. 555–558. [7] D. Mandal, P. Mandal, T. K. Bhattacharyya, “Spur reducing architecture of frequency synthesizer using switched capacitors”, IET Circuits Devices Systems, vol. 8, no. 4, pp. 237–245, 2014. [8] S. Bruss, R. Spencer, “A 5-GHz CMOS type-II PLL with low KVCO and extended fine-tuning range”, IEEE Transactions on Microw, vol. 57, no. 8, pp. 1978–1988, 2009. [9] C.Y. Kuo, J.Y. Chang, S. I. Liu, “A spur-reduction technique for a 5-GHz frequency synthesizer”, IEEE Transactions on circuits and systems, vol. 53, no. 3, pp. 526–533, 2006. [10] C. M. Hung, K. O. Kenneth, “A fully integrated 1.5-V 5.5-GHz CMOS phase-locked loop”, IEEE Journal of Solid-State Circuits, vol. 37, no. 4, pp. 521–525, 2002. [11] Z. Bereber, S. Kameche, E.Benlchelifa, “High tolerance of charge pump leakage current in Integer-N PLL frequency synthesizer for 5G networks”, Simulation Modelling Practice and Theory, vol. 95, pp. 134-147, 2019. [12] W. B. Wilson, U. Moon, K. R. Lakshmikumar, L. Dai, “A CMOS self-calibrating frequency synthesizer”, IEEE Journal of Solid-State Circuits, vol. 35, no. 10, pp. 1437–1444, 2000. [13] T. C. Lee, W. L. Lee, “A spur suppression technique for phase-locked Frequency synthesizers”, IEEE International Solid-State Circuits Conference (ISSCC), Feb 2006, Kuala Lumpur, Malaysia, pp. 2432-2433. [14] H. Gan Ko, W. Bae, G. Jeong, D.kyoon, “Reference Spur Reduction Techniques for a Phase-Locked Loop,” IEEE Access, vol. 7, pp. 38035–38043, 2019. [15] J. Sharma, H. Krishnaswamy, “A 2.4-GHz Reference-Sampling Phase-Locked Loop That Simultaneously Achieves Low-Noise and Low-Spur Performance”, IEEE Journal of Solid-State Circuits, vol. 45, no. 5, pp. 1407–1424, 2019. [16] C. Thambidurai, N. Krishnapura, “On pulse position modulation and its application to PLLs for spur reduction”, IEEE Transactions on Circuits and Systems, vol. 58, no. 7, pp. 1483–1496, 2011. [17] J. Choi, W. Kim, K. Lim, “A spur suppression technique using an edge interpolator for a charge-pump PLL”, IEEE Transactions on Circuits and Systems, vol. 20, no. 5, pp. 969–973, 2012. [18] J. F. Huang, J. L. Yang, R.Y. Liu, “The 1-V 2.4 GHz low-spur Fractional-N frequency synthesizer chip design with exploiting randomly selected PFD and subsampling charge pump”, Microwave and Optical Technology Letters, vol. 57, no. 1, pp. 61-66, 2015. [19] T.W. Liao, C. M. Chen, J. R. Su, C. C. Hung, “Random Pulse Width Matching Frequency Synthesizer with Sub-Sampling Charge Pump”, IEEE Transactions on Circuits and Systems, vol. 59, no. 12, pp. 2815– 2824, 2012. [20] C. F. Liang, H. H. Chen, S. I. Liu, “Spur-suppression techniques for frequency synthesizers”, IEEE Transactions on Circuits and Systems, vol. 54, no. 8, pp. 653–657, 2007. [21] M. Elsayed, A. Latif, E. Sinencio, “A Spur-Frequency-Boosting PLL with a -74 dBc Reference-Spur Suppression in 90 nm Digital CMOS”, IEEE Journal of Solid-State Circuits, vol. 48, no. 9, pp. 2104-2117, 2013. [22] S. Jahangirzadeh, A. Amirabadi, A. Farrokhi, “Low spur frequency synthesizer using randomly shifted reference spur to higher frequencies,” International Journal of Electronics, 107 (12), 2044-2067, 2020.
[23] N. Xi, F. Lin, T. Ye, “A Low-Spur and Intrinsically Aligned IL-PLL with Self-Feedback Injection Locked RO and Pseudo-Random Injection Locked Technique”, IEEE Transactions on Circuits and Systems, pp.1-10, 2020.
[24] D. Biswas, G. S. Javed, K. S. Reddy, “5-GHz Integer-N PLL with spur reduction sampler”, IEEE Electronics Letters, vol. 55, no. 23, pp. 1217–1220, 2019.
[25] M. A. Karami, M. Ansarian, S. Aghli-Moghaddam, “A Novel Ring Voltage Controlled Oscillator utilizing Miller Effect”, Tabriz Journal of Electrical Engineering, vol. 47, no. 1, pp. 221-228, 2017.
[26] Abbas Nasri, Mostafa Yargholi, “Design of Class C VCO with Frequency Tripler for 17.8 – 19.19 GHz”, Tabriz Journal of Electrical Engineering, vol. 48, no. 4, pp. 1841-1852, 2018. [27] N. Kamal, S. Al-Sahrawi, D. Abbott, “An accurate analytical spur model for an Integer-N phase-locked loop”, IEEE 4th International Conference on Intelligent and Advanced Systems (ICIAS), June 2012, Kuala Lumpur, Malaysia, pp. 659-664. [28] Y.W. Chen, Y.H. Yu, Y. J. Emery Chen, “A 0.18- m CMOS dual-band frequency synthesizer with spur reduction calibration”, IEEE Microwave and Wireless Components Letters, vol. 23, no. 10, pp. 551–553, 2013.
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آمار تعداد مشاهده مقاله: 256 تعداد دریافت فایل اصل مقاله: 191 |
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