مقابله با اشکال همشنوایی در شبکه‌های روی تراشه با ارائه یک کدینگ اجتناب از همشنوایی سه مقداره

[1]        A. Cilardo and E. Fusella, “Design automation for application-specific on-chip interconnects: A survey,” Integration, the VLSI Journal, vol. 52, pp. 102-121, 2016.

[2]        B. E. Cheah, J. Kong, and K. C. Yong, “Crosstalk study of high speed on-package interconnects for multi-chip package,” in the Proceedings of the IEEE International Symposium on Electromagnetic Compatibility,  2016, pp. 340-350.

[3]        B. Fu and P. Ampadu, “Error control for network-on-chip links,” Springer, USA, 2012.

[4]        I. P.Vaisband, R. Jakushokas, M. Popovich, A. V. Mezhiba, S. KöseEby and G. Friedman, “Shielding Methodologies in the Presence of Power/Ground Noise,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 19, n. 8, pp. 1458 - 1468, 2011.

[5]        Q. J. Lu, Z. M. Zhu, Y. T. Yang, and R. X. Ding, “Analysis of propagation delay and repeater insertion in single walled carbon nanotube bundle interconnects,” Microelectronic Journal, vol. 54, pp. 85–92, 2016.

[6]        Y. Hu, X. Cui, and Y. Ran, “Bus partitioning technique with crosstalk avoidance code,” in the Proceedings of the IEEE International Conference on Solid-State and Integrated Circuit Technology, pp. 112-117, 2013.

[7]        M. Mehri and N. Masoumi, “A thorough investigation into active and passive shielding methods for nano-VLSI interconnects against EMI and crosstalk,” International Journal of Electronics and Communications, vol. 69, no. 9, pp. 1199-1207, 2015.

[8]        ITRS, “The International Technology Roadmap for Semiconductors-2015 edition,” [Online]. Available: http://www. public.itrs.net, 2015.

[9]        K. Hirose and H. Yasuura, “A bus delay reduction technique considering crosstalk,” in the Proceedings of the Conference on Design, Automation and Test in Europe, pp. 441-445, , 2010.

[10]     W. N. Flayyih, K. Samsudin, and S. J. Hashim, “Adaptive multibit crosstalk-aware error control coding scheme for on-chip communication,” IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 63, no. 2, pp. 166-170, 2016.

[11]     M. Mutyam, “Fibonacci codes for crosstalk avoidance,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 20, no. 10, pp. 1899-1903, 2012.

[12]     ITRS, “The international technology roadmap for semiconductors – 2012 edition,” Available at: http://www. public.itrs.net, 2012.

[13]     G. Chen, S. Nooshabadi, “Analysis and design of serial error correction code with crosstalk avoidance technique,” in the Proceedings of the IEEE International Conference Canadian Conference on Electrical and Computer Engineering, pp. 1-4, 2017.

[14]     S. Liu, P. Reviriego, L. Xiao “Reducing the cost of triple adjacent error correction in double error correction orthogonal latin square codes,” IEEE Transactions on Device and Materials Reliability, vol. 69, no. 9, pp. 269- 271, 2016.

[15]     S.Lee, “Adaptive error correction in Orthogonal Latin Square Codes for low-power, resilient on-chip interconnection network,” Microelectronics Reliability, vol. 53, no. 3, pp. 509- 511, 2013.

 [16] غلامرضا زارع فتین، سعیده نبی پور، جواد جاویدان،" طراحی یک دیکدرBCHبهینه جهت افزایش اطمینان در ذخیره سازی اطلاعات و تصحیح خطا در حافظه‌های فلش،" نشریه مهندسی برق دانشگاه تبریز، مقاله 27، دوره 46، شماره 3 - شماره پیاپی 77، پاییز 1395،  صفحه 319-331.

 [17] محمدامین ثابت سروستانی، بهنام قوامی، محسن راجی،"کاهش نرخ خطای نرم چندگانه مدارهای ترکیبی مبتنی بر اندازه‌گذاری دروازه‌ها بر مبنای پارامتر حساسیت،"  نشریه مهندسی برق دانشگاه تبریز، مقاله 9، دوره 47، شماره 2 - شماره پیاپی 80، تابستان 1396، صفحه 445-456.