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مقاومسازی الگوریتمهای رمزنگاری در داخل FPGA به کمک PLL | ||
مجله مهندسی برق دانشگاه تبریز | ||
مقاله 12، دوره 49، شماره 2 - شماره پیاپی 88، مرداد 1398، صفحه 601-612 اصل مقاله (1003.65 K) | ||
نویسندگان | ||
وحید رشتچی* ؛ سید حمید رضا موسوی | ||
دانشکده مهندسی برق و کامپیوتر - دانشگاه زنجان | ||
چکیده | ||
امروزه اشتراک اطلاعات در سیستمهای مخابراتی و کامپیوترها نیازمند امنیت بسیار بالایی است. در این میان، حملات کانال جانبی همواره بهعنوان یکی از چالشهای امنیتی در رمزنگاری سیستمها میباشد، که برای حمله به ادوات رمزنگاری ازجمله کارتهای هوشمند بکار میرود. در این مقاله هدف ارائه طرح جدیدی برای مقاومسازی الگوریتمهای رمزنگاری است که بهصورت سختافزاری در FPGA پیاده شدهاست. اساس این طرح استفاده از حلقه فاز قفل شده PLL در الگوریتمهای رمزنگاری AES میباشد که با به همزدن میزان توان مصرفی و زمانهای اجرای بخشهای مختلف الگوریتم، مقاومت الگوریتمهای رمزنگاری را در برابر حملات توان بالا میبرد. این روش از دو تکنیک masking و hiding برای حفاظت کلید خصوصی رمزنگاری استفاده میکند، طرح پیشنهادی در تکنولوژی TSMC 65nm شبیهسازی شده و موفقیت قابلتوجه نشان داده است، بهطوریکه توانسته است در رمزنگاری AES با هزینه سربار 13% در فضای اشغالی CMOS و افزایش 15 درصدی توان مصرفی، تنها فرکانس کاری را به اندازه 2% کم کرده و امکان به دست آوردن کلید صحیح برای حملهکننده را بسیار سخت نماید. همچنین، روش پیشنهادی بر روی FPGA پیادهسازی شدهاست و نتایج رضایتبخشی بر روی تعداد قابل قبولی از نمودار توان بهدست آمدهاست. | ||
کلیدواژهها | ||
استاندارد رمزنگاری پیشرفته (AES)؛ پردازش توان تفاضلی؛ اندازهگیری توان؛ آرایه گیتهای قابلبرنامهریزی(FPGA) | ||
مراجع | ||
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