انسداد میدان الکتریکی جانبی از نواحی درین و سورس جهت بهبود اثرات کانال کوتاه در افزاره Nano-SOI

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[4] S. Rajabi, M. Saremi, H. J. Barnaby, A. Edwards, M. N. Kozicki, M. Mitkova, D. Mahalanabis, Y. Gonsalez-Velo, A. Mahmud, Static impedance behavior of programmable metallization cells, Solid State Electron. vol. 106, pp. 27-33, 2015.

[5] Mohammad K. Anvarifard, Increase in the scattering of electric field lines in a new high voltage SOI MESFET, Superlattices Microstruct. vol. 97, pp. 15-27, 2016.

[6] J. Ervin, A. Balijepalli, P. Joshi, V. Kushner, J. Yang, T.J. Thornton, CMOS compatible SOI MESFETs with high breakdown voltage, IEEE Trans. Electron Devices, vol. 53, pp. 3129–3135, 2006.

[7] J. Ervin, A. Balijepalli, P. Joshi, V. Kushner, J. Yang, T.J. Thornton, CMOS compatible SOI MESFETs with high breakdown voltage, IEEE Trans. Electron Devices, vol. 53, pp. 3129–3135, 2006.

[8] M. Rahimian, Ali A. Orouji, A novel nanoscale MOSFET with modified buried layer for improving of AC performance and self-heating effect, Mater. Sci. Semicond. Process. vol. 15, pp. 445–454, 2012.

[9] M. Jagadesh Kumar, Anurag Chaudhry, Two-Dimensional Analytical Modeling of Fully Depleted DMG SOI MOSFET and Evidence for Diminished SCEs, IEEE Trans. Electron Dev. vol. 51, pp. 569-574, 2004.

[10] W. Long, H. Ou, J.-M. Kuo, and K. K. Chin, Dual material gate (DMG) field effect transistor, IEEE Trans. Electron Devices, vol. 46, pp. 865–870, 1999.

[11] Mohammad K. Anvarifard, Ali A. Orouji, Voltage difference engineering in SOI MOSFETs: A novel side gate device with improved electrical performance, Materials Science in Semiconductor Processing, vol. 16, pp. 1672-1678, 2013.

[12] M. Zareiee, A novel high performance nano-scale MOSFET by inserting Si3N4 layer in the channel, Superlattices and Microstructures, vol. 88, pp. 254-261, 2015.

[13] H. Shahnazarisani, S. Mohammadi, Simulation analysis of a novel fully depleted SOI MOSFET: Electrical and thermal performance improvement through trapezoidally doped channel and silicon–nitride buried insulator, Physica E: Low-dimensional Systems and Nanostructures, Vol. 69, pp. 27-33, 2015

[14] مهسا مهراد، میثم زارعی، «ارائه ساختار نوین ترانزیستور اثر میدان سیلیسیم روی عایق دو گیتی با پنجره اکسید در درین گسترده شده بهمنظور کاربرد در تکنولوژی نانو»، مجله مهندسی برق دانشگاه تبریز، جلد 47، شماره 2، صفحات 80-86، 1396.

[15] حامد نجفعلی زاده، علی لصغر اروجی، « طراحی ساختاری از ترانزیستور ماسفت دوگیتی با به کارگیری دو ماده، اکسید هافنیوم  HFO­₂ و سیلیسیم ژرمانیوم SiGe در کانالی از جنس سیلیسیم DM-DG»، جلد 47، شماره 1، صفحات 79-84، 1396.

[16] ATLAS User’s Manual: 2-D Device Simulator, SILVACO International, Santa Clara, CA, USA, 2012.

[17] J. Chen, J. Luo, Q. Wu, Z. Chai, T. Yu, Y. Dong, and X. Wang, A tunnel diode body contact structure to suppress the floating-body effect in partially depleted SOI MOSFETs, IEEE Electron Device Lett., vol. 32, no. 10, pp. 1346–1348, 2011.